Track and hold amplifier

ABSTRACT

A track and hold amplifier for use in adc-converters comprises in succession an input buffer, a pn-junction switch and a hold capacitor. A feedback is provided between the hold capacitor and the input buffer and means are provided to disable the feedback during the hold mode.

[0001] The invention relates to a track and hold amplifier comprising aninput buffer for receiving an input signal and for transferring thereceived input signal to a first terminal of a pn-junction switch asecond terminal of which is connected to a hold capacitor, and means tosupply a switching signal to said first terminal of the pn-junctionswitch for translating the buffered input signal through the switchingpn-junction to the hold capacitor during a track mode and for blockingthis transfer during a hold mode. A track and hold amplifier of thiskind is known from the article “A 12-b, 60-Msample/s Cascaded Foldingand Interpolating ADC”, by P. Vorenkamp and R. Roovers in IEEE Journalof Solid State Circuits, Vol 32, No 12, December 1997, Pages 1876-1886.

[0002] A track and hold amplifier is often used in the input of ananalog to digital converter to separate the sampling operation from thequantization operation. Present day multistep AD-architecture has anumber of comparators, which do not operate simultaneously. However, itis necessary that all the comparators see the same analog signal value.The function of the track and hold amplifier is to determine the voltagelevel of the input signal at the sampling instant of the track and holdamplifier, and to maintain this value during a certain time period, soas to ensure that all comparators see the same analog input value.Moreover, each comparator has input capacitance which causes the inputsignal level to be compared to reach its correct level only after somedelay. Therefore, without a track and hold amplifier, the comparatorwould compare an incorrect signal level, especially at higher signalfrequencies. The track and hold amplifier samples the input signal atthe correct value and maintains this value during the hold mode, so thatthe comparator-input has enough time to reach its correct signal levelfor subsequent quantization.

[0003] A drawback of the abovementioned prior art track and holdamplifier is that during the track mode larger currents flow into thehold capacitor, especially at higher signal frequencies. These largercurrents flow into the holding capacitance through the pn-junctionswitch. This results in large non linear signal distortion andconsequently in incorrect signal sampling. The signal distortion, causedby the pn-junction, may easily reach values of some tens of millivolts,which is too large for modem applications, where the total signalamplitude is not more than 1 Volt.

[0004] The present invention has for its object to overcome thisdrawback of the prior art track and hold amplifier and the track andhold amplifier of the present invention is therefore characterized by afeedback connection from the second terminal of the pn-junction switchto the input buffer and means to enable the feedback during the trackmode and to disable the feedback during the hold mode. The feedback fromthe second terminal of the pn-junction switch to the input bufferreduces the signal distortion at this second terminal and shifts thedistortion to the first terminal of the pn-junction switch, where itdoes not harm. However, this feedback has a detrimental effect on thehold feedthrough of the amplifier because the input signal could reachthe holding capacitance through this feedback path. Therefore thefeedback is disabled during the hold mode. The feedback may for instancebe disabled during the hold mode by cutting off the current through theinput buffer. This however has inter alia the drawback that the inputimpedance of the amplifier varies with the track and hold switchingsignal. A preferred arrangement according to the invention is thereforecharacterized in that said means to enable the feedback during the trackmode and to disable the feedback during the hold mode comprises a secondpn-junction switch within said feedback connection and second means tosupply the switching signal to the second pn-junction switch.

[0005] The said second means to supply the switching signal to thesecond pn-junction switch may cause a large voltage jump on the part ofthe feedback connection between the input buffer and the secondpn-junction switch. This voltage jump may cause interference of thevoltage of the hold capacitor through the junction capacitance of thesecond pn-junction switch. It is a further object of the invention tolimit this interference and the track and hold amplifier of theinvention may be further characterized by clamping means connected tothe part of the feedback connection between the input buffer and thesecond pn-junction switch.

[0006] It is another object of the invention to provide a track and holdamplifier which is characterized by resistive means between the secondterminal of the first pn-junction switch and the hold capacitor forincreasing the stability of the feedback path.

[0007] These and other aspects of the invention will be furtherexplained with reference to the attached Figures. Herein shows:

[0008]FIG. 1 an embodiment of a track and hold amplifier which is knownin the art, FIG. 2 a first embodiment of a track and hold amplifieraccording to the invention and

[0009]FIG. 3 a second embodiment of a track and hold amplifier accordingto the invention.

[0010] The prior art track and hold amplifier of FIG. 1 comprises aninput buffer I_(B) with a first emitter-coupled transistor pair T₁-T₂and a common emitter current source S₁. The transistor T₂ has itscollector- and base-electrodes interconnected and a collector loadcurrent source S₂. This well known arrangement transfers an input signalvoltage V_(i), applied to the base electrode of transistor T₁, to asubstantially identical voltage at the base electrode of transistor T₂,especially when the current of the source S₁ is twice the current ofsource S₂. The output of the input buffer is coupled, through aconnection point P to the base electrode of a switching emitter followertransistor T₃. The emitter electrode of this transistor T₃ is connectedto a hold capacitor C_(H) and to the input of an output buffer O_(B).This output buffer comprises a second emitter-coupled transistor pairT₄-T₅ with a common emitter current source S₃. The transistor T₅ has itscollector- and base-electrodes interconnected and a collector loadcurrent source S₄. Moreover a DC-shift transistor T₆ with interconnectedcollector and base electrode, is inserted between the collectorelectrode of transistor T₅ and the current source S₄. Theinterconnection between the current source S₄ and the DC-shifttransistor T₆ constitutes the output O of the track and hold amplifier.

[0011] The arrangement further comprises a third emitter-coupledtransistor-pair T₇-T₈ with common emitter-current-source S₅. Thecollector-electrode of transistor T₇ is connected to the base-electrodeof the emitter follower transistor T₃ and the collector electrode oftransistor T₈ is connected to the emitter electrode of transistor T₃.The base electrodes of the transistors T₇ and T₈ receive a track andhold switching puls T/H which makes the base electrode of the transistorT₈ high and the base electrode of the transistor T₇ low during the trackmode and, inversely, the base electrode of transistor T₈ low and that oftransistor T₇ high during the hold mode.

[0012] In operation, during the track mode the current of current sourceS₅ flows through the transistor T₈ into the emitter electrode of theemitter follower transistor T₃. Consequently, the signal voltage V_(i),which is applied through the input buffer to the base electrode oftransistor T₃, appears at low impedance and one V_(be) junction voltageshift lower at the hold capacitor C_(H) and at the input of the outputbuffer O_(B). Equally as with the input buffer, especially when thecurrent of source S₃ is twice the current of source S₄, the currentsthrough the transistors T₄ and T₅ are equal, so that the base (andcollector) voltage of transistor T₅ is equal to the base voltage oftransistor T₄. The buffered signal is shifted upwardly one V_(be)junction voltage by transistor T₆ in order to compensate for thedownward voltage shift caused by the emitter follower transistor T₃, andthereafter applied to the output O of the amplifier. Consequently,during the track mode, the output signal of the track and hold amplifieris substantially equal to the input signal.

[0013] During the hold mode, the current of source S₅ flows through thetransistor T₇ and pulls the voltage of point P down. Now the transistorT₃ is switched off and the base voltage of transistor T₄ andconsequently the output voltage at terminal O is determined by thevoltage of the hold capacitor at the level which it had at the end ofthe track mode. It may be noted, that the voltage drop at point P biasesthe emitter-base junction of transistor T₂ in cutoff direction.Therefore the function of the input buffer, apart from lowering theimpedance level at the input during the track mode, is also to isolatepoint P from the input signal source during the hold mode, so that thevoltage of point P is allowed to be pulled downwardly.

[0014] The arrangement of FIG. 1 additionally has a clamping transistorT₉, whose base electrode is connected to the output terminal O and whoseemitter electrode is connected to point P. During the track mode thevoltage at point P and the voltage at the output terminal O aresubstantially equal so that the clamping transistor T₉ is cut off andinoperative. During the hold mode, however, if point P is pulled downmore than one V_(be) junction voltage, the transistor T₉ becomesconducting thereby limiting the voltage drop at point P to one V_(be)junction voltage. This measure is taken because a too large voltage dropat point P would result, through the parasitic base-emitter capacitanceof transistor T₃, in a too large transient pulse in the output voltage.

[0015] A drawback of the prior art arrangement of FIG. 1 is that duringthe track mode the signal variations cause large currents flowing intothe hold capacitor C_(H), especially at the higher signal frequencies ofe.g. 20 Mhz. These large currents flow into the hold capacitor throughthe emitter follower transistor T₃ and thereby cause, across thenon-linear base-emitter junction of this transistor large and non-linearvoltage variations, so that the track and hold amplifier actuallysamples and holds a distorted signal level.

[0016] The arrangement of FIG. 2, in which corresponding circuitelements as in FIG. 1 have the same reference numerals, seeks to avoidthe above described distortion. In this arrangement the base electrodeof transistor T₂, in stead of being coupled to the collector electrodeof this transistor, is coupled, through a transistor T₁₀, to the emitterelectrode of transistor T₃, so that a feedback loop is constituted fromthe collector electrode of transistor T₂ through the base-emitterjunction of transistor T₃ and through the transistor T₁₀ to the baseelectrode of transistor T₂. While the input buffer seeks to make thebase voltage of T₂ substantially equal to the input voltage, thisfeedback loop seeks to make the emitter voltage of transistor T₃substantially equal to the base voltage of transistor T₂, so that, as aresult, the emitter voltage of transistor T₃ represents the inputvoltage substantially without distortion. In fact, the distortion whichis caused by the emitter-base junction of transistor T₃ appears now atthe base electrode of his transistor in stead of at the emitterelectrode.

[0017] When the base electrode of transistor T₂ and the emitterelectrode of transistor T₃ would be directly connected to each other, aproblem arises during the hold mode. During this mode the transistor T₃is cut off so that the base electrode of T₂ now follows the hold voltageof the hold capacitor C_(H). When the input voltage V_(i) rises duringthe hold mode the base emitter junction of transistor T₂ blocks, howeverwhen the input voltage decreases the base emitter junction of transistorT₂ conducts a large current which (de)charges the hold capacitor so thatthe hold voltage is distorted. This undesired hold mode feedthrough isprevented by the insertion of a pn-junction switch in the feedback pathbetween the emitter electrode of T₃ and the base electrode of T₂. In thearrangement of FIG. 2 this switch is implemented by the transistor T₁₀,which has interconnected base- and collector electrodes and thereforeoperates as a diode. To operate this switch the arrangement of FIG. 2further comprises a current source S₆ connected to the collector/base oftransistor T₁₀ and a fourth emitter coupled transistor pair T₁₁-T₁₂ withan emitter current source S₇, with the collector of transistor T₁₁connected to the base electrode of transistor T₁₀ and the collectorelectrode of transistor T₁₂ connected to the emitter electrode oftransistor T₁₀. Equally as in the case of the transistor pair T₇-T₈, thebase electrodes of the transistors T₁ and T₁₂ receive a track and holdswitching pulse T/H. During the track mode, the current of source S₆flows through the transistors T₁₀ and T₁₂, so that the base emitterjunction of transistor T₁₀ is conductive. On the other hand, during thehold mode and provided the current of source S₇ is larger than thecurrent of source S₆, the current of source S₆ flows through thetransistor T₁₁, the base-emitter junction of transistor T₁₀ is cut offand the aforementioned undesired hold mode feedthrough is prevented.

[0018] It may be observed that the original track mode distortion by theconductive base-emitter junction of transistor T₃ in the arrangement ofFIG. 1, is not replaced in the arrangement of FIG. 2 by a similardistortion due to the conductive base-emitter junction of T₁₀. This isbecause through the conductive base-emitter junction of T₁₀substantially only DC current flows and the AC signal-current flowingthrough this junction is negligible.

[0019] It is further observed, that, during the hold mode, theconductive transistor T₁₁ pulls down the voltage of point Q, i.e. theinterconnection of the base electrodes of the transistors T₂ and T₁₀.This pull down may be limited by a further clamping transistor T₁₃ whichhas its base electrode connected to the output terminal O and itsemitter electrode to point Q. This voltage pull down of point Q does notonly cut off the transistor T₁₀ but also the transistor T₂, which givesa further reduction of the hold mode feedthrough. If the voltage pulldown at point Q is not sufficiently large to cutoff the transistor T₂for all values of the input voltage Vi, this pull down can be increasedby inserting a resistor (R₁) of appropriate value in the emitter lead ofclamping transistor T₁₃.

[0020] A further resistor R₂ is included between the emitter electrodeof the switched emitter follower transistor T₃ and the hold capacitorC_(H). The function of this resistor is threefold:

[0021] The emitter of transistor T₃ represents an inductive impedancewhich, with the large hold capacitor C_(H) constitutes an LC-loop. Theresistor R₂ damps out undesired ringing of this LC-loop.

[0022] The resistor R₂ filters KT/C noise from reaching the holdcapacitor C_(H).

[0023] The resistor R₂ separates the hold capacitor C_(H) from thefeedback loop T₃, T₁₀, T₁₂. This improves the stability of this feedbackloop.

[0024] An alternative arrangement is shown in FIG. 3, in which againcorresponding elements as in FIG. 1 and 2 have the same referencenumerals. As in the arrangement of FIG. 2, this has also a feedbackconnection from the emitter electrode of transistor T₃ to the baseelectrode of transistor T₂, however in this arrangement the switchingtransistor T₁₀ fails. In order to disable the feedback during the holdmode, the current source S₁ of the input buffer has been replaced by anemitter-coupled transistor pair T₁₄-T₁₅ with common emitter source S₈.The collector electrode of transistor T₁₅ is connected to the commonemitter electrodes of transistor pair T₁-T₂ and the collector electrodeof transistor T₁₄ is connected to the positive supply. A further currentsource S₉ is connected between the positive supply and the commonemitters of T₁ and T₂. The base electrodes of transistor pair T₁₄-T₁₅receive the track and hold switching pulse T/H, which makes the baseelectrode of T₁₅ high during the track mode and which makes the baseelectrode of T₁₄ high during the hold mode.

[0025] In operation, during the track mode, with the transistor T₁₅conducting and the transistor T₁₄ cut off, the coupled emitterelectrodes of T₁ and T₂ carry the current of source S₈ minus the currentof source S₉. With the current of S₈ greater than the current of S₉, thedifference current has the same function as the current of source S₁ inthe arrangements of FIGS. 1 and 2 and the transistors T₁ and T₂ operateas usual for buffering the input signal. During the hold mode, thetransistor T₁₅ is cut off and the transistor T₁₄ conducts the current ofthe source S₈. The current of the source S₉ now lifts the potential ofthe two emitter electrodes of T₁ and T₂, thereby cutting off these twotransistors. With the transistor T₂ cut off, the feedback from theemitter electrode of transistor T₃ to the transistor T₂ is disabled andthe hold mode feedthrough through this connection is largely prevented.Therefore, in the arrangement of FIG. 3 the transistor T₂ has taken overthe function of the transistor T₁₀ in the arrangement of FIG. 2. Thesimultaneous cut off of the transistor T₁ assists in the reduction ofthe hold mode feedthrough.

[0026] In order to reduce the amplitude of the voltage pulse at thecommon emitter electrodes of the transistor pair T₁-T₂, a clampingtransistor (diode) T₁₆ with interconnected base- and collectorelectrodes, is connected between the common emitters of the input bufferT₁-T₂ and the common emitters of the output buffer T₄-T₅. During thetrack mode, both common emitters have substantially the same potential,namely the input signal voltage V_(i) minus one V_(be) junction voltage.The clamping transistor T₁₆ conducts during the hold mode and preventsthat the voltage of the emitters of T₁ and T₂ rises above the inputsignal voltage V_(i). In the arrangement of FIG. 3 the output terminal Ois connected between the transistors T₅ and T₆, because in thisarrangement, due to the absence of a transistor T₁₀, the voltage at theinput of the output buffer is one V_(be) junction voltage shift higherthan in the arrangement of FIG. 2.

[0027] In practice, the arrangement of FIG. 2 may be preferred over thearrangement of FIG. 3 because the latter consumes less energy from thedc supply. Moreover a disadvantage of the arrangement of FIG. 3 is thatthe input impedance of the arrangement changes with the track and holdswitching because the transistor T₁ is conducting during the track modeand cut off during the hold mode.

1. A track and hold amplifier comprising an input buffer (I_(B)) forreceiving an input signal and for transferring the received input signalto a first terminal (P) of a pn-junction switch (T₃) a second terminalof which is connected to a hold capacitor (C_(H)), and means (T₇, T₈) tosupply a switching signal to said first terminal (P) of the pn-junctionswitch for translating the buffered input signal through the switchingpn-junction to the hold capacitor during a track mode and for blockingthis transfer during a hold mode, characterized by a feedback connectionfrom the second terminal of the pn-junction switch (T₃) to the inputbuffer (I_(B)) and means to enable the feedback during the track modeand to disable the feedback during the hold mode.
 2. A track and holdamplifier as claimed in claim 1 , characterized in that said means toenable the feedback during the track mode and to disable the feedbackduring the hold mode comprise a second pn-junction switch (T₁₀) withinsaid feedback connection and second means (T₁₁, T₁₂) to supply theswitching signal to the second pn-junction switch (T₁₀).
 3. A track andhold amplifier as claimed in claim 2 , characterized by clamping means(T₁₃, R₁) connected to the part of the feedback connection between theinput buffer (I_(B)) and the second pn-junction switch (T₁₀).
 4. A trackand hold amplifier as claimed in claim 1 , characterized by resistivemeans (R₂) between the second terminal of the first pn-junction switch(T₃) and the hold capacitor (C_(H)) for increasing the stability of thefeedback path.